AMD said it is supplying programmable radio SoCs to Meta Platforms as part of a program to reduce the cost of building sprawling wireless networks that can handle the deluge of data from the metaverse.
The Santa Clara, California-based chip maker is offering its Xilinx-designed Zynq UltraScale RFSoC to Meta’s Evenstar program, which promotes the new Open RAN technology for building 4G and 5G base stations.
AMD's partnership with Meta follows its $49 billion acquisition of Xilinx, which closed in February.
All About that Base Station
A base station—also called the radio access network (RAN)—is a set of hardware modules that are usually mounted on poles or buildings and connect phones or other devices to a wireless network. The RAN includes a radio unit (RU) that contains radio-frequency (RF) transceivers and other ICs to convert and amplify RF signals. The radio unit is generally located close to or integrated directly into the antennas on a base station.
One of the other key components of a base station is the distributed unit (DU), which houses the baseband processor that runs L1 (or PHY) functions of the RAN protocol stack—or shares the load with the RU. The final component is the central unit (CU), which runs inside the carrier's cloud data centers and controls several of the DUs.
According to industry analysts, today's base stations are full of proprietary interfaces, so telcos are forced to buy all of the components from a single vendor in a pre-integrated hardware and software bundle.
Open RAN allows telcos to mix and match “best-of-breed” hardware and software for base stations instead of buying everything from the likes of Ericsson, Huawei Technologies, Nokia, or other vendors. Experts warn we are years out from a completely open model for building base stations, but the Open RAN standard could give telcos a lot more flexibility and make pricing for hardware more competitive.
Open RAN allows for flexible partitioning network functions—a concept called disaggregated RAN. AMD said the Zynq RFSoC gives telcos the flexibility to divide baseband processing between the radio and DUs.
Adaptable SoC, Hard IP
The RU houses a range of components, including the RF transceiver and digital front end (DFE), which is the building block that AMD is targeting with the UltraScale RFSoC family. The DFE is one of the more critical stages in the base station. It serves as a bridge between the RF transceiver and RF chips to the baseband modem on the other side used to handle the PHY (or L1) signal-processing jobs in the radio.
The DFE can reconfigure the channels in the radio in real-time and carry out pre-processing on radio signals from the base station’s antennas, then clarify them before sending them to the baseband processor in the DU.
With its heterogeneous architecture, the UltraScale RFSoC can serve as a complete software-defined radio that can meet a range of requirements for 4G and 5G networks based on millimeter-wave and sub-6-GHz bands.
AMD said the UltraScale RFSoC has a combination of hardened logic for RF functions while leaving a degree of programmable logic—the same type of logic at the heart of Xilinx's FPGAs—so that its customers can differentiate themselves from other telecom firms.
With the ability to run in 4G LTE and 5G modes at the same time in a single radio, the chip has a wideband RF transceiver with eight transmit and eight receive channels with up to 400 MHz of instantaneous bandwidth (IBW).
Hardware accelerators at the heart of the Xilinx RFSoC can carry out digital upconversion (DUC) and downconversion (DDC) to shift the baseband signal up or down to different frequencies. The digital-to-analog (DACs) and analog-to-digital converters (ADCs) inside support 7.125 GHz of direct-RF bandwidth. The hardened logic can handle other chores such as crest-factor reduction (CFR) to reduce noise in radio transmissions.
Lastly, the signal processing unit in the Xilinx-made RFSoC offers resampling and other radio functionality.
Open RAN's Future
5G radios require high-end chips that not only meet bandwidth, power, and cost efficiencies for widespread deployment in the field, but they also must have the flexibility to fit new 5G standards such as Open RAN.
Integrating everything on a single compact chip lessens the hardware's power and heat dissipation. The use of hardened IP helps keep costs in check, while programmable logic leaves the door open for design flexibility.
The wide instantaneous bandwidth allows it to support carrier aggregation (CA) with up to eight carriers for every antenna in the base station. More data pipes within the same radio help reduce costs at the system level.
There is also a hardware accelerator for digital predistortion (DPD), which is widely used to increase the linearity of RF power amplifiers. This is a soft-core processor that customers can adapt to their specific requirements, AMD said.
The RFSoC can be paired with a wide range of energy-efficient power amplifiers, including advanced wideband GaN power amplifiers that help boost power efficiency and density in 4G LTE and 5G RANs. Used as a millimeter-wave intermediate-frequency (IF) transceiver, it offers up to 1,600 MHz of bandwidth.
The AMD-Meta tie-up builds on efforts by other telecom and technology firms that are backing Open RAN.
Open RAN is projected to account for up to 15% of the total market for RAN infrastructure by 2026, according to market research firm Dell’Oro Group.