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Intel Works with Arm to Adapt Mobile Chip Designs to Its Fabs

April 14, 2023
The effort will help ensure Arm’s mobile chip designs are compatible with Intel’s future process nodes.

Intel said it would team up with Arm to make it easier for mutual customers to use Intel’s foundry services to fabricate Arm-based mobile processors and other chips.

The companies announced a long-term agreement that will make sure Arm’s CPU cores and other IP are compatible with Intel’s 18A node—the most advanced process technology on its roadmap due to launch in 2025.

They said the focus at first is on optimizing mobile systems-on-chip (SoCs), where Arm’s CPU cores are essential building blocks. But, according to a statement, the companies also are open to optimizing chip designs for automotive, IoT, data centers, aerospace, and other areas.

The deal is the latest step in CEO Pat Gelsinger’s plan to restore Intel’s leadership in manufacturing high-end logic chips. Under his “IDM 2.0” strategy, he’s trying to take back the crown it lost to TSMC and other rivals after years of missteps by Intel management. If it can execute the strategy, this will help Intel roll out products that are more competitive with the likes of AMD, NVIDIA, and even Apple.

One of the keys to the recovery plan involves building a contract chipmaking business, opening up its process technologies to rivals—more specifically suppliers of mobile chips. Intel launched the independent unit, dubbed Intel Foundry Service (IFS), in mid-2021.

While the Santa Clara, California-based company is still in the early stages of building the business, Intel said Qualcomm and MediaTek, among others, are already planning to use its fabs to fabricate their future chip designs. Today, Samsung Electronics and TSMC are responsible for producing most of the world’s mobile chips.

"There is a growing demand for computing power driven by the digitization of everything, but until now fabless customers have had limited options for designing around the most advanced mobile technology,” said Gelsinger.

Additional Flexibility

Arm, which sells to virtually all of the world’s major semiconductor companies, also works closely with TSMC—Apple’s primary contract chip manufacturer—and other foundry providers to make sure that its mobile CPU cores and other IP are compatible with their processes.

While Intel competes with Arm to some extent—in data centers, personal computers, and other areas where Arm is threatening Intel—it makes sense if Intel wants companies to take its foundry business as seriously as that of TSMC and other rivals.

The tie-up offers more options to customers building mobile chip designs based on Arm CPU cores and other IP when choosing a foundry to mass-produce their products, and where geographically they want them to be fabricated.

Intel has been investing aggressively to boost its production capacity around the world, including large-scale projects in the U.S. and Europe, to help it meet demand down the road. The company said its “open system” foundry model brings more to the table than traditional wafer-fabrication services offered by other foundries, as it includes packaging, software, and access to its in-house chiplet technologies, too.

“As the demands for compute and efficiency become increasingly complex, our industry must innovate on many new levels,” said Rene Haas, CEO of Arm, which reportedly plans to IPO by the end of the year.

The partnership comes a year after Intel’s foundry business said it would invest $1 billion to help expand the ecosystem around the RISC-V instruction set architecture (ISA), the open-source alternative to Arm.

Hardware Innovation

Intel indicated that it plans to introduce innovations across the board when rolling out the 18A process technology.

One of the major improvements will involve the internal construction of the transistors. Instead of the FinFET that has dominated the last decade, Intel intends to use a “gate-all-around” (GAA) transistor design it calls the RibbonFET.

A FinFET is formed by placing fin-shaped protrusions inside the transistor, which acts as a tiny electronic switch. The component that turns the switch on and off—the “gate”—is draped over the fin, surrounding it on three sides and, thus, reducing the amount of current leaking out of the transistor. As a result, the FinFET wastes less power and creates less heat, which in turn improves its overall speed and efficiency.

The RibbonFET covers the transistor on all sides, rather than just some of the device, preventing even more current from leaking out of it. The company is counting on the RibbonFET to create faster, more efficient logic chips.

Another innovation Intel plans to include is a “backside power-delivery system" called PowerVia. Modern logic chips contain billions of transistors. Each one is covered by floors of interconnect wires that supply power to the transistor and send signals to other transistors on the IC, resembling stairwells in a miniature tower. These interconnects are formed by carving canals in silicon and filling them with copper wiring.

The tradeoff is that the wires used to route signals and relay power to the transistors are tangled together, increasing resistance that hurts power efficiency. PowerVia technology places the power rails behind the transistors instead of on the front of the silicon chip. Thus, power can be delivered directly to the transistors above rather than traveling the long way through floors and floors of interconnect wires.

PowerVia helps reduce resistance in the power-delivery system, and as a result, chips run cooler and more efficiently. The wires on the front of the wafer also are free to be used for signal routing, improving speeds.

As part of the deal, Intel and Arm said that they will undertake design technology co-optimization (DTCO), in which chip design and process nodes are optimized together to improve power, speed, area, and costs.

As system-level design takes on more importance, the companies also plan to create a mobile reference design and optimize everything about it, from applications and software to packaging and the silicon itself.

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