ISSCC 2004 Preview

Although the scope of presentations at next month’s IEEE International Solid-State Circuits Conference covers a wide range of technologies, this year’s theme of embedded systems highlights key technologies that are essential to create system-on-a-chip solutions. Leading the focus on embedded systems, three plenary presentations will examine various aspects of embedded design.

For starters, Nicholas Donofrio, a Senior Vice President of Technology and Manufacturing at IBM Corp., will discuss Processors and Memory: The Drivers of Embedded Systems Toward the Networked World. He will examine the drivers in intelligence and networking capabilities in consumer products, handsets, nontraditional IT products such as automobiles, washing machines, coffee makers, and a vast range of everyday products. Next, Nicky Lu, President and CEO of Etron Technology will discuss Emerging Technology and Business Solutions for System Chips. He will examine approaches for increasing the diversity of functions that can be integrated on the system chips and the trend towards multidimensional die integration.

To wrap-up the plenary presentations, Yrjo Neuvo, a Professor and Executive Vice President and CTO of Nokia Mobile Phones, will deliver his views of Cellular Phones as Embedded Systems. Today’s cellular phone is a combination of analog and digital technologies all integrated into a few system chips and controlled by complex programs. The addition of new features, improved performance, and power challenges will be analyzed from an embedded systems viewpoint. He will also examine terminal trends and their impact on power economy, radio technologies and multiradio concepts, technological implementations, and integration challenges.

In keeping with the embedded theme, several non-volatile memory papers in Session 2 will examine embedded flash and ferroelectric storage schemes. Virage Logic, in paper 2.4, will detail a low-density flash technology (sub 16 kbits) that can be manufactured on a standard CMOS process with an integrated SRAM array. In paper 2.5, designers from Saifun Semiconductors show off a 256-Mbit flash memory with embedded microcontroller that controls the programming and erase functions, and in paper 2.6, Matsushita Electric Industrial Co. details a 0.9-V one-transistor/one-capacitor embedded ferroelectric storage cell.

Embedded SRAMs are also the focus of several papers in Session 27. In paper 27.2, Hitachi, SuperH, and Renesas Technology show the design of a 300-MHz 1-Mbit SRAM module that has a low leakage current of just 25 µA. Following that, Intel will show off a 9-Mbyte third-level cache that it cointegrates with the Itanium 2 processor. Detailed in paper 27.3, the cache uses three transistor types with differing threshold voltage levels to optimize performance and minimize leakage currents. Researchers at Stanford University will, in paper 27.5, describe an embeddable reconfigurable SRAM block that can operate at 1.1 GHz with a 1.8-V supply.

The first four papers in Session 11 highlight several advances in embeddable DRAM, with paper 11.1 focusing on a 0.6-V embedded DRAM block that operates at 205 MHz. The 16-Mbit memory block, developed jointly by United Memories and Sony, consumes just 39 mW when active. Paper 11.2 also details a 16-Mbit embedded DRAM that can work at 312 MHz. Developed jointly by Renesas Technology and Daioh Electric, the block draws just 73 µW in its data-retention (standby) mode. IBM will present the next two embedded DRAM approaches in papers 11.3 and 11.4. In the first paper, researchers detail a 500-MHz multibank compilable DRAM macro implemented in a logic-based process. In the second paper, the other research team shows a high-speed—800-MHz—embedded DRAM that employs a transfer-gate structure that allows it to achieve a 3.2-ns cycle time.

In sessions that cover wireless systems, full transceivers on a chip will grab a lot of attention. In Session 5, NEC, Spirea, NewLogic, and Atheros (in conjunction with IRF Semiconductor and Stanford University), in papers 5.1 to 5.4, will show off multiband transceivers for 802.11a/b/g standards, all implemented in 0.18-µm CMOS, save for Atheros, which is using a 0.25-µm process.

Similar advances in Bluetooth transceivers will be detailed in Session 15, with papers 15.1 and 2 from Texas Instruments and Texas A&M University showing highly integrated solutions. In TI’s presentation, engineers will detail a discrete-time Bluetooth receiver, while Texas A&M will unveil a dual-mode 802.11b/Bluetooth receiver.

Many other presentations at the conference will focus on embeddable building blocks—high-speed I/O buffers, a-d converters, voltage-controlled oscillators, digital signal processors, and more. Several sessions will also examine emerging technologies. Session 16, for instance, will detail Polymer Thin-Film Transistors developed by Seiko Epson, Cut-and-Paste Organic FETs Customized For Artificial Skin by the University of Tokyo, and a Non-Volatile Programmable Solid Electrolyte Nanometer Switch from NEC and NIMS.

Want to Go? The 2004 IEEE International Solid State Circuits Conference will take place at the San Francisco Marriott Hotel, February 15-19. For detailed program and registration information, go to www. isscc.org.