Fast Serial Link Offers Low-Cost Scalability

Aug. 18, 2003
As processors, supporting logic, and memory chips get faster, wide parallel buses consume too much power and area, especially in low-cost systems. To help cut chip pin counts and power, many...

As processors, supporting logic, and memory chips get faster, wide parallel buses consume too much power and area, especially in low-cost systems. To help cut chip pin counts and power, many companies have developed single- or multiple-channel interfaces that can transfer data at rates from a few hundred kilobits per second to hundreds of megabits per second.

Texas Instruments has been using its VLYNQ interface as a proprietary solution on its own DSL, cable and voice broadband processors, digital media processors, and OMAP media processor chips. Cost-competitive licensing agreements will let companies integrate it into their own chips.

The VLYNQ interface is a daisy-chained, serial, full-duplex peer-to-peer communications scheme that operates at clock speeds up to 125 MHz. It can be scaled to deliver from one to eight transmit/receive (T/R) signal pairs and a common clock line for all the signal lines (17 pins plus an optional clock-request pin). The interface requires only one-fifth the silicon area of the PCI Express serial interface. Two VLYNQ blocks are required if the chip is part of a daisy chain.

Data transferred over the interface is 8B/10B encoded and packetized so there is about a 20% overhead for the encoding and additional overhead for the packetization. When clocked at 125 MHz, a single T/R pair then delivers an effective data throughput of about 73 Mbits/s (for single, 32-bit word transfers), while a dual T/R pair implementation delivers 146 Mbits/s, and a maximum eight-channel version delivers 584 Mbits/s. In-band flow-control lets the interface independently throttle the transmit and receive data streams.

If data packets contain four or 16 words, some of the overhead is eliminated. So on a single channel, data bursts of four words per packet can deliver an effective throughput of 133 Mbits/s. With 16 words per packet, the throughput goes up to 178 Mbits/s. With the maximum eight channels, an effective throughput of over 1400 Mbits/s can be achieved with 16 words per packet.

See associated figure

Texas Instruments Inc.www.ti.com
About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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