System Compiler Speeds Front-End IC Design

Oct. 1, 2001
Said to bring fully automated, accurate timing and block information to front-end integrated IC design, the TOPOMO physical system compiler integrates and automates block partitioning, block placement, global routing, and synthesis into one tool. The

Said to bring fully automated, accurate timing and block information to front-end integrated IC design, the TOPOMO physical system compiler integrates and automates block partitioning, block placement, global routing, and synthesis into one tool. The system auto-partitions a multi-million-gate design into system-level blocks, based on actual timing and area to achieve rapid timing convergence. It concurrently places blocks, calculates and creates a netlist that has been driven by global interconnects. It also identifies long and short wires and correctly triggers global synthesis and timing optimizations. A one-year subscription costs $200,000. For further information, call GET2CHIP, INC., San Jose, CA. (408) 501-9600.

Company: GET2CHIP, INC.

Product URL: Click here for more information

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