The ARCtangent-A5 adds the ARCompact 16-bit compressed instruction set. It allows a mix of 16- and 32-bit instructions, providing a 30% reduction in code size. Instructions are aligned on 16-bit boundaries. The A4 and A5 aren't binary compatible, but there's a conversion program that takes A4 binaries and generates A5 binaries. The core can be very small (10.5 kgates), though this includes no cache.
Besides making adjustments to the processor core, the ARChitect design tool can select peripherals. It's more of an SoC design tool than a processor configuration tool. Although the 32-bit architecture must be retained, almost anything else can change, including registers and interfaces. www.arccores.com
Xtensa is remarkably easy to use. It shows an estimate of performance and real estate costs during the design process. Tradeoffs often mean giving up a megahertz or two of clock speed for features like wider buses or larger caches. More features translates into more power consumption. Tensilica's approach offers the advantage of estimates made up front rather than after a design has been implemented.
Xtensa has a conventional processor architecture and instruction set. The instruction set implemented on a particular system reflects the target attributes selected when the system is designed.
Tensilica's TIE (Tensilica Instruction Extension) technology enables implementation of custom instructions. Although it's similar to in-struction extensions in other core designs, TIE provides a more flexible environment for taking advantage of core resources.
Real-time operating-system support includes VxWorks and ATI Nucleus Plus. C and C++ compilers, assemblers, and debuggers for these platforms are generated with a system design. www.tensilica.com