A high-performance processor means nothing if data can't be moved on and off a chip very quickly. Most designers have access to core-specific on-chip interconnects, such as Arm's AMBA. But off-chip connections need more standards-based solutions like ISA, PCI, and PCI-X.
Unfortunately, these standards are running out of steam for high-performance CPUs. New, faster packet-oriented standards like HyperTransport, RapidIO, and PCI Express appear to be the solution. HyperTransport and RapidIO target processor and controller interconnects, while PCI Express aims at controller-to-peripheral interconnects. HyperTransport and RapidIO links are being placed into new processor designs. This meshes well with the plethora of bridge chips between these interfaces and other standards, such as PCI, PCI-X, PCI Express, IDE, SCSI, and so forth.
These new interconnects don't require additional glue hardware, making embedded systems design significantly easier. They also employ tunneling architectures that allow a device to forward data for other devices. Moreover, switch fabrics can be employed when performance and expandability requirements demand them.
Note that although processor bus widths have been climbing, interestingly, interconnect bus widths have been falling with bit serial being as low as it can go.
