Hybrid Verification Tool Unravels Digital IC Designs

May 12, 2003
The speed of static is melded with the accuracy of dynamic in a transistor-level crosstalk and timing analysis tool that unearths critical paths.

High-end digital IC designs pose numerous verification challenges. For one, static analysis methods alone will often fail to turn up potentially fatal timing problems that are due to nanometer effects. For another, too many simulation vectors exist for exhaustive analysis of timing behavior.

To address the needs of digital verification in the nanometer age, Nassda offers its Hanex timing and crosstalk analysis tool. Developed to provide accurate transistor-level analysis of digital designs at process technologies of 130 nm and below, the tool uses a hybrid of static and dynamic timing analysis to solve design issues at the block level.

Hanex finds critical paths in combinational, latch/flip-flop, and dynamic logic, simulating the entire critical path simultaneously. In doing so, it considers voltage-dependent capacitance, Miller capacitance, and nonlinear input slopes for greater accuracy. It also fits well into existing design flows (see the figure).

Among its timing checks, Hanex verifies setup and hold times for sequential logic, including crosstalk effects, using dynamic clock-tree analysis. It provides a more realistic assessment of circuit behavior than can be achieved with static methods. Traditional static timing analyzers approximate coupling capacitors using grounded capacitors, making for results that degrade as process technologies shrink. Hanex performs crosstalk analysis using dynamic simulation on coupling caps for more accuracy. It accurately analyzes the impact of adjacent nets on circuit performance.

Further, the tool's hybrid capabilities provide accurate clock net timing simulation. Clock nets are automatically identified and traced starting with a user-defined clock source. After the nets are back-annotated with interconnect RC networks (from third-party extraction software), Hanex simulates the entire clock net with precise fanout loading, storing clock arrival time and slope at every clock sink.

Hanex will be available in June with time-based licenses starting at $72,000. It's supported on Sun Solaris, HP-UX, Windows NT/2000/XP, and Linux platforms.

Nassda Corp.

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