Next Nexus Delivers Debug Data

July 7, 2003
An optional pin can cut transfer overhead for higher data-transfer rates.

The Nexus 5001 Forum enhanced its IEEE ISTO 5001-1999 debug specification with an upward-compatible implementation that provides higher throughput and increased efficiency. The 2003 revision incorporates new connector specifications, especially for ruggedized environments. Ron Stence, senior strategic marketing and systems engineer of Motorola and the vice chairperson of the Nexus Forum, also indicated that the Nexus 5001 Forum has improved the bylaws so that all members can cross-license any Nexus technology. The standard itself is open and processor-independent, but the implementations will be vendor-specific.

Nexus adds an auxiliary port to the standard JTAG port. The auxiliary port provides a wider, higher-bandwidth data transfer conduit. Using additional pins in the port provides higher throughput. It also uses the JTAG port in Nexus-specific ways to implement various classes of services.

The most basic, Class 1, provides features similar to standard JTAG implementations. However, it sets certain minimum requirements, such as the need for at least two hardware breakpoints. Debugging halts the chip like normal JTAG products.

Class 2 is where the real action starts, with real-time monitoring. It also adds instruction tracing and more sophisticated watchpoints. As with each class, it's a superset of the prior.

Data tracing comes in Class 3. Services also include the ability to read and write memory and I/O while the processor continues to run. This makes the system design more complex but significantly improves the debugging capabilities.

Finally, Class 4 delivers features found in many in-circuit emulators (ICEs), like the ability to remap memory and I/O ports. This is especially useful when simulating peripherals. It can also be used to provide other applications running on the testing system with access to shared memory.

In addition to the four classes, Nexus defines a number of optional features. These include starting memory substitution upon watchpoint occurrence, monitoring data reads while the processor runs in real-time, port replacement and port sharing, and the ability to transmit data values for acquisition.

CHANGES IN 2003 Nexus implementations may now have two Messaging Start/End-Out (MSEO) pins. This allows back-to-back data transfers, speeding delivery of memory data or trace information. Time stamping and message synchronization provides more accurate information for tracking down time-related problems. Data trace information has also been improved, so data size is known.

Numerous enhancements were made in the program trace feature. For example, indirect branches are now flagged, making it easier to differentiate indirect branches from exception handling. Additional messages are included for improved branch tracking. The format of the trace data was changed to eliminate redundant addressing information and thereby increase throughput.

With its new features, Nexus is landing in processors that run in environments requiring real-time debugging, such as automotive and process control. It may even wind up in established proprietary debugging architectures such as ARM ( and Intel's Pentium ( The improved debug facilities will simplify a developer's job by exposing more information.

Class 1 Services Features
Basic run control Static debugging Breakpoints Single step
Set breakpoints and watchpoints
Two breakpoints minimum
Static memory and I/O access
Device identification
Class 2
Instruction trace Watchpoints Watchpoints
Ownership Trace
Program Trace
All Class 1 features
Monitor process ownership
in real time
Real-Time program tracing
Class 3
Data Trace
Read/write access
Data trace
Real-time read/write
All Class 2 features
Access memory and I/O in
real time
Real-Time data tracing
Class 4
Memory and port
Memory substitution
Port replacement
All Class 3 featuers
Start traces on watchpoint
occurrence program execution
from Nexus port

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