Multicore Chip Handles Broadband Packet Processing

May 7, 2009

The Octeon II from Cavium Networks handles packet traffic on high-speed serial links such as 10-Gbit Ethernet, Serial RapidIO (SRIO), and PCI Express (PCIe) v2. The chip family is scalable from two to six MIPS cores augmented with a collection of accelerators from the Security Vault secure key storage to RAID 5/6 support for storage applications (see the figure).

The CN63xx can incorporate hardware accelerators for encryption and packet analys i s . The Hyper Finite Automata (HFA) support r egular expressions to scan packets. The HFA’s 16-bit wide d y n ami c RAM memory controller is independent of the main 72-bit Hyperaccess DDR3 memory controller. An 8-Tbyte/s Hyperconnect crossbar switch links the memory controller and cores. Pricing starts at $59.

CAVIUM NETWORKSwww.caviumnetworks.com

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