Chip Handles Deep Packet Inspection At 20 Gbits/s

July 27, 2009
Cavium Networks’ NITROX DPI CN17xx L7 Content processor is designed to deliver rule-based packet inspection and processing at full line rates from 4 to 20 Gbits/s. The scalable system can handle millions of flows while providing deterministic, low-latency

Cavium Networks’ NITROX DPI CN17xx L7 Content processor is designed to deliver rule-based packet inspection and processing at full line rates from 4 to 20 Gbits/s. The scalable system can handle millions of flows while providing deterministic, low-latency operation. Its 8x PCI Express links can tie it to Cavium Networks Octeon II network processors or to other high-performance processors such as x86-compatible platforms. Also, the NITROX DPI supports POSIX- and Perl-compatible regular expression patterns. Its Hyper Finite Automata Threading Engines (HTE) implement rule-set caching and walking technology to deliver deterministic, low-latency performance. Plus, there are no rule-set size or flow limits. The HTEs are compatible with the ones found in the Octeon II and support match length reporting. The chips incorporate on-chip caches and DDR2 memory controllers, which support up to 4 Gbytes of off-chip pattern memory. Pattern compression reduces space requirements by a factor of 15. Support is provided for SNORT and other open-source intrusion detection systems. The chip is also available on a PCI Express adapter.

Cavium Networks

www.caviumnetworks.com

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