Tool Supports HDL Project Management, Design Entry & Simulation

Version 3.5 of Active-HDL is a tool that provides users of 1-million-gate-plus FPGAs with a means of performing line-by-line source code debugging of their HDL code. Active-HDL gives users a fully IEEE 1076-87/93-compliant VHDL simulator that can be “bolted on” to any FPGA vendor’s design flow.At the same time, Active-HDL is a full design environment that manages, tests and simulates complex FPGA and ASIC designs. It affords the flexibility of being able to use any synthesis or silicon vendor’s place-and-route tools through TCL/TK scripts providing seamless integration to any third-party software. Three product configurations are available: Standard, Plus and Expert. All include an HDL editor, block-diagram editor, state-machine editor, automatic testbench generation, VHDL simulation, design management and structural simulation.