Different Takes On New Server Tech

Sept. 13, 2012
Intel did not have any new earth shattering architectures at the Intel Developer Forum but there was a lot of server action from partners and around the show.

There was an interesting collection of new technology on and around the 2012 Intel Developer Forum (IDF) in San Francisco. Of course, Apple tried to steal some thunder with its iPhone 5 announcement (see Apple Announces iPhone 5: Big Surprise!) but another LTE phone with a multicore Arm processor is not quite as interesting. Luckily there was a bit more to see nearby. I'll add the link to the video interviews I did ath IDF on Engineering TV when they have been posted. It takes a little longer to get them done.

Splitting a Supermicro

Super Micro Computer's (Supermicro) new Fat Twin architecture (Fig. 1) addresses scalability and maintainability as packages shrink. It essentially splits the size of its rack mount systems in half and puts them back into the rack in two wide or Fat Twin configuration.

Figure 1. Supermicro's Fat Twin architecture splits the rack putting a processing blade on each side of the rack mount systems.

The approach makes sense compared to 1U systems because the smaller width fits the motherboard design as well as providing sufficient disk drive support in a hot swappable package. The main rack can accept different combinations of Fat Twin module/blades that may be 1U high or more. Larger versions provide more board, disk and compute capacity. It provides a more flexible approach for system designers and handles the latest x86 micros.


Xilinx is looking to put its high end Virtex-7 FPGA into an Intel processor socket (Fig. 2). It has added suppport for a single Quick Path Interconnect (QPI) channel that is the same mechanism that Intel processors use for high speed chip-to-chip communication.

Figure 2. Xilinx puts its Virtex 7 FPGA into an Intel processor socket via QPI support allowing it to be part of a multicore solution with coherent cache support.

QPI provides a cache coherent processor link allowing processors to share memory. Normally a multiple processor Intel motherboard has two or four processor socketes and each processor has multiple QPI interfaces. The current FPGA implementation utilizes a single channel. It is possible to support multiple channels but this would be for motherboards with more than two sockets and may be available in the future since the QPI interface is a soft core in the FPGA.

The FPGA is mounted on a board that fits within the keep out area of a processor socket. This area is normally needed for the large cooling heatsink. The FPGA needs a heatsink and fan too but it is much smaller. On the other hand, the FPGA board has a good bit of power management hardware around the FPGA chip. There are two sockets as well that expose the high speed SERDES that are typically linked to interfaces like 10 Gbit Ethernet. A cable and a PCI Express card provide the sockets for these interfaces. The PCI Express interface is only used to acquire power for the board. It does not actually use any of the PCI Express data lines.

Dynamic FPGA configuration is theoretically possible but not something that is currently available or needed for most target applications. The FPGA is programmed via JTAG and most installations will have the FPGA programmed for a fixed application. The platform will likely target specialized FPGA applications but these can make for very interesting servers.

Hypercube Expands For More Storage

Obviouslyy AMD was not at IDF but it too had a number of announcements this week. This included the SeaMicro SM15000 server (Fig. 3) that extends the hypercube Freedom Supercomputer Fabric outside the box for additional disk storage.

Figure 3. The SeaMicro SM15000 server extends the hypercube fabric outside the box for additional disk storage.

The system connects 64 boards together with a SeaMicro fabric. The architecture supports Sandy Bridge Xeons (see Microserver Has 64 Sandy Bridge Xeons In 10U Rack) boards or boards with multiple 64-bit Atom processors (see 512 64-bit Atom Cores In 10U Rack). The new system can also support 8-core AMD Opteron processors using the soon to be released Piledriver cores that handle up to 4 Tbytes of DRAM.

The system also has connections to disk arrays and 1G and 10G Ethernet. These are contained inside the box and employ FPGA controllers that provide a fabric interface as well as custom peripheral controllers that provide management support. The SM15000 differs from earlier versions because it brings out 16 channels of the fabric into boxes designed for up to 1408 disk drives supporting up to 5 petabytesof storage and providing the simplicity of DAS (direct access storage) but with the sharing attributes of SAN or NAS. These boxes also employ FPGAs to provide access to the disk drives allowing the same management approach to be used for internal and external devices.They also support RAID 0, 1, 5, 6 and 10.

The move outside the box allows support for a significant number of SAS or SATA drives. Like the move from Atom to Xeons, the new SeaMicro platform provides significantly more storage for those applications that need it.

About the Author

William Wong Blog | Senior Content Director

Bill Wong covers Digital, Embedded, Systems and Software topics at Electronic Design. He writes a number of columns, including Lab Bench and alt.embedded, plus Bill's Workbench hands-on column. Bill is a Georgia Tech alumni with a B.S in Electrical Engineering and a master's degree in computer science for Rutgers, The State University of New Jersey.

He has written a dozen books and was the first Director of PC Labs at PC Magazine. He has worked in the computer and publication industry for almost 40 years and has been with Electronic Design since 2000. He helps run the Mercer Science and Engineering Fair in Mercer County, NJ.

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