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Dual-Issue Multicore SOC Handles Soft Peripherals

April 17, 2015
XMOS has doubled the number of instructions per clock cycle with its new, multicore xCORE-200 platform. It also delivers gigabit Ethernet support for under $5.
1. The XMOS xCORE-200 platform uses a switch to connect multiple cores together. A core can wait for an event providing instant response without interrupt handlers.

More and more multicore solutions are now targeting embedded applications, but XMOS has been pushing hard, real-time, multicore solutions for quite some time. The latest xCORE-200 platform has up to 32 lightweight, 32-bit cores and a 1-Gbit Ethernet interface (Fig. 1). The family has up to 2 Mbytes of flash and 1 Mbyte of SRAM and does 64-bit transfers. XMOS developers take a different approach to real-time parallel processing; cores are designed to wait for events instead of using interrupt routines that have latency and overhead issues.

The xCORE-200 uses a dual-issue instruction decode providing improved performance compared to the original xCORE series. Each core can run applications like a conventional microcontroller, but they are also designed to be dedicated to an activity (such as handling high-speed communication). The hardware response ports allow very efficient bit-banging, soft peripheral solutions (Fig. 2). They can be configured from 1- to 32-bits.

2. The I/O for the xCORE-200 is designed to minimize overhead for soft peripherals.

A core can stop and wait for an event so there is no interrupt overhead. The large number of cores allows numerous interfaces to be supported by a single chip. A full duplex serial can be implemented using a core to transmit and receive, and another to coordinate these functions. It is also possible to run multiple tasks on a core supported by a hardware scheduler that can handle core and task priorities. This programming approach can actually be easier compared to interrupt handlers, especially when timing considerations are taken into account.

The xCONNECT switch provides communication between cores. Some xCORE-200 chips allow these switches to be interconnected. Cores can communicate with each other regardless of where they are located. The switch is also deterministic. This capability is significant when combined with the soft peripherals and deterministic memory access.

The chips are built around tiles that have multiple cores. Each tile has local SRAM and one has flash memory attached to it. Each tile also has OTP memory to support secure boot and encryption keys.

3. The xCORE-200 eXplorer Kit has a 16-core XE216-512 chip, 6 servo interfaces and a 1-Gbit Ethernet port.

Developers can check out the new chips using the xCORE-200 eXplorer Kit (Fig. 3), which has a 2000 MIPS, 16-core XE216-512 chip with 512 Kbytes of SRAM, 6 servo interfaces and a 1 Gbit Ethernet port. It has a High-Speed USB interface in addition to a 3D accelerometer and magnetometer.

XMOS provides xTIMEcomposer Studio, an Eclipse-based IDE, that includes fully standards-compliant C and C++ compilers. There is additional support for XMOS parallel processing and communication services, but this is similar to the runtime support for any microcontroller. 


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