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Multiple Big Cores Plus NPU Target Top-of-the-Line Smartphones

Sept. 22, 2025
MediaTek’s Dimensity 9500 takes smartphones to the next level with a multi-large-core compute engine and compute-in-engine NPU.

MediaTek’s Dimensity 9500 (see figure) builds on the success of the Dimensity 9400+. The 9500 includes a compute engine based on large-core Arm applications. Also in the mix are a high-performance GPU and a computing-in-memory (CIM) NPU that support Low-Rank Adaptation (LoRA) on-device training for large language models (LLMs). LoRA is used to fine-tune models for customization of artificial-intelligence (AI) models for users of high-performance smartphones.

The CPU array incorporates a single, 4.21-GHz C1-Ultra core, three 3.5-GHz C1-Premium cores, and four 2.7-GHz C1-Pro cores. These share a 16-MB L3 cache. Single-core performance is 32% more than the Dimensity 9400 while lowering power by 37%. The scalable matrix extension (SME 2) instructions provide a 57% improvement when doing object detection.

The GPU, an Arm Mali G1-Ultra that targets high-performance gaming platforms, embeds the Arm Ray Tracing Unit version 2 (RTUv2). The GPU can deliver 120 frames/s with ray-tracing support. The GPU supports Vulkan 1.4, access to the ray-tracing pipeline, and the Unreal Engine 5.5/5.6 for gaming.

An ISP Imagiq 1190 image signal processor complements the GPU. The system supports image stabilization and can capture images up to 200 Mpixels. On the display side, the SoC supports 1-nit ultra-dark screen technology. Its adaptive display technology is designed to improve viewing in dark environments.

The NPU 990 is the second-generation neural processing unit, which supports Bitnet 1.58-bit models in addition to hardware compression technology. It includes acceleration hardware to support transformers. The NPU can handle 128K-token-long text processing as well as working with 4K image resolution at 60 frames/s in portrait mode. It can handle 3B LLM output.  

The 30-billion-transistor chip is built on TSMC’s 3-nm process. The chip will be mated with LPDDR5-10667 DRAM and flash memory via a x4 UFS 4.1 interface — twice the speed of prior versions.

On the communication side, cellular, Wi-Fi, and Bluetooth support address the latest features like 5CC multi-carrier aggregation. Smart signal strength identification and Wi-Fi-assisted cellular communication allows platforms to deliver the highest bandwidth.

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF
About the Author

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.

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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.  

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