Post-Quantum Crypto Secures FPGA Boot

Altera has finally spun off from Intel, allowing Altera to focus on FPGA chips and tools. Its latest release is the Agilex 5 D-Series that fits in the middle of its FPGA portfolio (Fig. 1). The Agilex FPGAs can also incorporate hard Arm CPU logic like the dual-core Arm Cortex-A55 plus dual-core Arm Cortex-A76 hard logic. The Agilex 9 family supports Direct RF technology.

Using Post-Quantum Cryptographic Secure Boot

The Agilex portfolio consists of RAM-based FPGAs, in which the configuration is contained in serial memory that’s read into RAM at boot time (Fig. 2). Secure boot has been a feature, but it utilized pre-quantum cryptography algorithms. This was fine until quantum computing started to move toward practical implementations.

While quantum computing isn’t mainstream, it’s moving in that direction. Once adopted, it will make breaking most pre-quantum cryptography algorithms trivial, which is spelled out in the video on NIST-adopted new post-quantum cryptography algorithms last year.

The Agilex 5 D-Series provides post-quantum cryptography (PCQ) secure boot in addition to performance and capacity improvements. The feature is essentially transparent to developers, as was the pre-quantum incarnations. Developers only need to be concerned with creating the boot configuration. The hardware handles the boot process and its matching crypto support.

Higher Performance and Capacity of the Agilex 5 D-Series

PCQ secure boot is a significant new feature of Agilex 5 D-Series, but it’s far from the only new aspect. It bumps up the number of logic table units (LTUs) at the top end from 644K to 1.6M LUTs. The internal memory bandwidth has been doubled and the 2.5X improvement in logic extends to the DSP and artificial-intelligence (AI) support as well as internal memory.

The external DDR5 memory interface was also bumped up to 5,600 Mtransfers/s while LPDDR5 speeds were increase to 5,500 Mtransfers/s. The FPGAs support 4K/8K video processing as well.

FPGA Development Tools Streamline Design Processes

Altera announced updates to its design tools, including Quartus Prime (Fig. 3). This FPGA design tool supports the entire Agilex portfolio. Improvements were made to the compiler, which runs 27% faster than its predecessor. It also optimizes designs employing Altera’s Adaptive Logic Module (ALM), initially introduced in the earlier Stratix FPGA family.

A key component of Quartus Prime is Visual Design Studio (Fig. 4). It employs a drag-and-drop design process with enhanced productivity features to cut creation time from days to hours. Designers can use it to combine IP quickly. Projects that would take days can often be completed in hours utilizing Visual Design Studio.