Xilinx And Synopsys Collaborate On Tool Flow For Platform FPGAs

Dec. 3, 2001

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., now includes Synopsys LEDA register-transfer-level...

David Maliniak

Those tools join the existing flow of Synopsys' VCS or Scirocco for simulation, Synopsys' FPGA Compiler II for synthesis, and the Xilinx Integrated Software Environment (ISE) 4.1i. This flow was designed to reduce development time while helping to ensure that products meet specifications when realized with Xilinx's Virtex-II Platform FPGAs.

The new FPGA flow lets designers use tools and strategies previously only available for ASICs. It's the most comprehensive support available for Xilinx's Virtex II FPGAs. Designers create a specification in VHDL or Verilog. Synopsys' LEDA checks HDL code for good workmanship, correctness, and performance, applying a Virtex-II rule set jointly developed with Xilinx.

The RTL is simulated using a high-speed simulator, such as Synopsys' VCS or Scirocco. Next, the design is synthesized with Synopsys' FPGA Compiler II, which optimizes the high-level logic description into the Virtex-II architecture. Xilinx's ISE 4.1 software performs implementation .

Once implemented, Virtex-II designers can save valuable development time by performing static timing and functional verification on the design before testing it in the lab. Xilinx supplies scripts and libraries to enable the use of the PrimeTime and Formality ASIC verification tools. PrimeTime statically analyzes and verifies the post-layout timing of the Virtex-II device and provides comprehensive feedback to the designer using time-saving features, such as bottleneck- and mode-analysis. Formality uses formal mathematical techniques to quickly ensure that the design is functionally equivalent to the RTL specification.

All Synopsys products are available now. For details, go to www.synopsys.com. The Xilinx design rules for the Synopsys LEDA HDL Checker can be downloaded from www.synopsys.com/products/leda/leda.html.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.