FPGA Design Flow Takes Simulink Code Into Synthesis

Thanks to collaboration between The MathWorks and Mentor Graphics, MathWorks’ Simulink HDL Coder users gain a smooth path into synthesis. Mentor’s Precision Synthesis tool now supports HDL generated by Simulink HDL Coder, enabling users to directly create optimized netlists for FPGAs. Simulink HDL Coder generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models, embedded Matlab code, and Stateflow charts. Precision Synthesis provides comprehensive language support (including SystemVerilog), an advanced ASIC prototyping flow, and automatic incremental synthesis. It also offers powerful design-analysis capabilities, allowing designers to cross-probe between multiple views and perform interactive static timing "what-if" analyses. All users of both Simulink HDL Coder and Mentor’s Precision suite for FPGA design benefit from this collaboration, provided that they are using Precision 2006a or newer. Precision Synthesis is available at a starting price of $20,200. Mentor Graphics
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