System architects generally turn to application-specific integrated circuits (ASICs) when designing ICs for high-volume, high-performance applications. Yet the development of such ASICs calls for expensive design tools. It also invites high development costs and extended time to market. To conquer these problems, Altera recently introduced its third-generation structured ASIC: the 90-nm HardCopy II family.
The HardCopy II structured ASICs were created as an alternative to standard-cell ASICs in order to meet the complex requirements of next-generation systems (FIG. 1). Essentially, a HardCopy II structured ASIC is a non-reprogrammable device that's seamlessly migrated from a Stratix II field-programmable-gate-array (FPGA) prototype. Thanks to this FPGA-prototyping capability, the HardCopy II family claims to offer the lowest risk and fastest time to market of any structured ASIC. According to the company, these ASICs deliver a clock speed of over 350 MHz, densities of up to 2.2 million ASIC gates, and 8.8 Mb of memory. Yet they cost only a fraction of the price of the FPGA prototype.
In fact, Altera offers the only structured-ASIC development process with seamless migration from a pin-compatible, functionally equivalent FPGA prototype. Compared to any other ASIC or structured-ASIC solution, this process promises to lower development risk and cost. Using both the Quartus II design software and the Stratix II FPGA family, designers can fully validate their designs in system and at speed. Before committing to silicon, designers can even test-market features and develop multiple variations of a design. Conveniently, designers also have the option to use their existing synthesis, verification, timing analysis, and logic-equivalency checking tools from Cadence, Mentor Graphics, Synopsys, and Synplicity.
After the engineers finalize their designs, the Quartus II design software automatically generates the files to hand off to Altera's HardCopy Design Center (FIG. 2). The HardCopy Design Center performs a turnkey migration of the design to a HardCopy structured ASIC. It delivers fully tested prototypes—a true drop-in replacement of the customer's FPGA—in eight to ten weeks.
To achieve such goals, the HardCopy II structured ASICs are built on a fine-grained architecture. This architecture is made up of transistor cells called HCells. The HCell-based architecture was designed to support a seamless FPGA migration while providing a much lower cost per ASIC gate. It also provides the lower-power, higher-performance, and higher-density benefits of 90-nm process technology.
A library of HCell macros preserves the seamless migration from the Stratix II adaptive logic module (ALM) to the HardCopy II HCell. Each HCell macro corresponds to a unique ALM configuration. Using the library, Altera's Quartus II design software maps each ALM into the HardCopy II logic fabric without resynthesis.
Each HardCopy II base array also contains hard intellectual-property blocks, such as RAM and phase-locked loops (PLLs). The hard IP that's embedded in the HardCopy II structured ASIC equals the IP in Stratix II FPGAs. In fact, the HardCopy II structured ASICs and Stratix FPGAs are built on the same 90-nm process. The resulting structured ASIC is functionally equivalent and pin compatible to the Stratix II FPGA in which the design was prototyped.
Compared to the FPGA prototype, however, it costs a tenth of the price and delivers twice as much performance. The structured ASICs also run at less than half the power consumption of the FPGA prototype. After all, only the utilized transistors draw current in the HardCopy II ASICs.
These structured ASICs are based on the feature sets that are found in the Stratix II FPGA family. Their features include low cost, as the HardCopy II devices deliver a lower cost-per-gate than the HardCopy Stratix devices. As far as memory is concerned, they offer up to 8.8 Mb of RAM. The HardCopy II structured ASICs claim to be richer in memory than competing structured ASICs. In addition, advanced external-memory interfaces allow designers to integrate external high-density SRAM and DRAM devices into complex system designs without degrading data-access performance.
In addition, the ASICs offer 118 receiver and 118 transmitter channels. They support source-synchronous signaling for data-transfer rates as high as 1 Gbps. To simplify printed-circuit-board (PCB) layout, the DPA circuitry in HardCopy II structured ASICs eliminates signal-alignment issues. Such issues arise when signals are being transmitted over long distances using source-synchronous signaling techniques.
The structured-ASIC family also addresses the high-performance needs of emerging I/O interfaces, such as the LVDS, LVPECL, and HyperTransport standards. The ASICs offer high-speed, differential-I/O supporting data rates of up to 1 Gbps. The high-bandwidth, single-ended I/O interface standards also are supported. These standards include SSTL, HSTL, PCI, and PCI-X. They address today's demanding system requirements. Regarding source-synchronous protocols, the HardCopy II structured ASICs support a range of high-speed interface standards like SPI-4.2, SFI-4, 10 Gigabit Ethernet XSBI, HyperTransport, RapidIO, NPSI, and UTOPIA IV for flexibility and quick time to market.
To ease the stress felt by designers, Altera's Quartus II software joins its third-party partners: Cadence, Mentor Graphics, Synopsys, and Synplicity. Together, they allow designers to reap the benefits of structured ASICs in less time and with minimal new training and investment. The Quartus II design software stands out because it offers a unified design flow for the development of both FPGAs and structured ASICs. If designers are using version 4.2 of the software, they can prototype a HardCopy structured ASIC up front. They also can use the same design flow, architecture, and tools as a Stratix II FPGA.
Designers can now begin prototyping HardCopy II designs in Stratix II FPGAs by using Quartus II version 4.2 software. The HardCopy II family has five members ranging in density between 1 million and 2.2 million ASIC gates. The first device, the HC230F1020, will be available in the third quarter of this year. All densities will be available by the first half of 2006. Pricing for the HardCopy II structured ASICs starts at $15 for the 1-million-gate HC210W at 100,000 quantities. NREs start at $225,000 for a full turnkey migration including the delivery of fully tested prototypes.