FPGA Has 90K Usable PLD Gates

Radiation hardened for low-earth orbit and launch applications, the new UT4090 RadHard FPGA features 90,000 usable PLD gates, data path speeds of 200 MHz, embedded SRAM and is targeted for QML Q and T compliance. The device is fabricated on 0.35µm four-layer CMOS process to maximize speed and reduce power. It is targeted to withstand total dose of 30 Krads tested to MIL-STD-883 Method 1019. A designed flip-flop eliminates the need for triple mode redundancy. The part interfaces with both 3.3V and 5V devices and is PCI-compliant with 3.3V and 5V busses. Advanced I/O capabilities include full JTAG boundary scan and registered I/O cells with individually controlled clocks and output enables. The device's 90,000 usable PLD gates are organized as 1,584 logic cells. Also, 22 dual-port RAM modules provide a total of 25 Kbits of dedicated SRAM in a variety of configurations. Software support is provided from QuickLogic. The device is packaged in a 208-pin Cerquad flatpack. Call for price. AEROFLEX UTMC, Colorado Springs, CO. (719) 594-8000.