FPGAs, popular as they are these days
for prototyping and/or production
runs, come with their own little quirks. One of those is the nagging tendency for functional errors to appear in
synthesis and subsequent optimizations.
To address this verification gap, OneSpin
Solutions has unleashed an equivalence
checker that supports all sequential operations performed by FPGA synthesis tools.
The 360 EC-FPGA () addresses the problem of comparing two design representations in which sequential optimizations
generate non-corresponding state structures. This is an unfortunate byproduct of
FPGA synthesis. Generally, the only way
around it has been to switch off optimizations performed in synthesis and go
through a great deal of manual scripting.
Otherwise, the optimizations invalidate
the working hypotheses of state correspondence used by conventional equivalence checkers, rendering them unable
to do the job.
With OneSpin's tool, FPGA users can go
ahead and leverage those optimizations
afforded by synthesis and verify the
design as is. Furthermore, the tool verifies
the entire FPGA as a flat netlist, which
enables the synthesis tools' most aggressive optimizations. It doesn't require the
"side files" generated by the synthesis
tools, which often aren't even validated by
equivalence checkers.
The tool verifies functional equivalence between the RTL code fed into synthesis and the post-synthesis FPGA
netlist. It does the same for the post-synthesis netlist and the post-place-and-route netlist. It supports all major FPGA
families from Altera and Xilinx as well as
netlists generated by Synplicity's Synplify
Pro and Altera's Quartus II FPGA synthesis tools.
The 360 EC-FPGA tool, which features
FPGA equivalence checking for Synplicity's Synplify Pro as well as Altera's Quartus II FPGA synthesis tools (in addition
to ASIC equivalence checking), is available now. Time-based licenses start at
$137,500.
OneSpin Solutions GmbH
www.onespin-solutions.com
