How do you get low-cost nonvolatile but reconfigurable FPGAs based on a 0.13-µm flash process? Easy. Lattice Semiconductor used the programmable-logic fabric developed for its EC family of SRAM-based FPGAs to craft the LatticeXP series, which loads the SRAM cells from an on-chip flash memory. The lowest-cost member of this FPGA line will cost less than $6 each in large volumes.
The five initial members of the LatticeXP family will pack from 3k to 20k lookup-table logic blocks and from 62 to 340 I/O pads. The chips also will contain 54 to 414 kbits of embedded memory and another 12 to 79 kbits of distributed memory. Two power-supply options are available for the chips. One supports 1.8-, 2.5-, or 3.3-V supplies, and the other provides 1.2-V support.
System functions implemented in the FPGAs can operate at clock speeds of up to 225 MHz. The system I/O pads can support a double-data-rate (DDR) 333-MHz memory interface, as well as I/O standards such as LVCMOS, LVTTL, PCI, LVDS, SSTL, and HSTL. Two or four dedicated phase-locked loops in the logic fabric help with frequency synthesis and clock alignment.
Because configuration data is stored in the on-chip flash, no external boot memory is needed and the FPGAs can self-configure in less than a millisecond, delivering an "instant-on" capability. Additionally, a portion of the FPGAs can be reprogrammed in real time during device operation. Users do not have to shut down the current application to update the logic configuration.
The FPGA configuration patterns can be developed on the company's ispLEVER design tools or on numerous third-party tools. To help shorten the design time, Lattice offers an intellectual-property library of popular complex logic functions.
The first device to be sampled, the XP10, packs 9700 LUTs, up to 244 I/O pins, and about 250 kbits of SRAM (total of both distributed and embedded). It costs $32.95 each in lots of 1000 units. In lots of 250,000 units, the projected price drops to less than $15.