FPGA Design Tool Suite Shortens Runtimes And Facilitates Incremental Design

    Jan. 18, 2007
    FPGAs are getting larger and larger, as evidenced by Xilinx's Virtex-5 devices, which are produced on a 65-nm process. Designers want faster runtimes for their FPGA tools as well as other features that let them reach timing closure more rapidly. Ve

    FPGAs are getting larger and larger, as evidenced by Xilinx's Virtex-5 devices, which are produced on a 65-nm process. Designers want faster runtimes for their FPGA tools as well as other features that let them reach timing closure more rapidly.

    Version 9.1i of Xilinx's Integrated Software Environment (ISE) offers those runtime improvements, along with what the company calls "SmartCompile technology," which offers a further runtime boost. In addition, SmartCompile allows exact preservation of unchanged logic while revised logic is incrementally recompiled.

    Overall runtimes for complex designs are reduced in ISE 9.1i by up to 2.5 times. But SmartCompile adds features such as SmartPreview, which permits pause-andresume functionality in the place-androute process to help identify timing-critical design regions.

    Another feature, SmartGuide, works closely with synthesis tools to ensure the use of consistent, repeatable names when resynthesizing small logic changes. As a result, reimplementation runtimes average from two times to four times faster.

    A third new feature under the SmartCompile umbrella is Partitions, which enables users to freeze the implementation of specified blocks within a design. These blocks are preserved down to the routing level. Yet another 2.5-times average runtime boost is garnered from Partitions when reimplementing portions of a design.

    ISE 9.1i is available now. Prices start at $2495. A full-featured, 60-day evaluation version is available for free. All versions support Windows 2000 and XP, Linux Red Hat Enterprise 3.0 and 4.0, and Solaris 2.8 and 2.9.

    Xilinx Inc.
    www.xilinx.com

    About the Author

    David Maliniak | MWRF Executive Editor

    In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.
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