Gate Array ASIC Takes Aim At FPGA-To-ASIC Conversions

Oct. 1, 1998

PCI-ready gate-array ASICs with input/output performance of 66 MHz is the order of the day for the Cutthroat family of devices. Clock-to-out performance is said to be in the 5-ns region.The growing demand in the communication and data processing markets for chips that support the 66-MHz PCI bus is a major impetus for the family's development. The devices are created using an enhanced version of the company's 3.3V, 0.5-µm digital CMOS process. The family also includes multiple speed indexes for all library components. This has been fine-tuned to work with the latest generation of synthesis products, resulting in high-performance silicon and area-efficient designs.

About the Author

Staff

Articles, galleries, and recent work by members of Electronic Design's editorial staff.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!