Crossover PLDs Challenge CPLDs And FPGAs

The MachXO family is described as a new class of crossover PLDs that support applications traditionally addressed by either high-density CPLDs or low-capacity FPGAs. The devices employ 130-nm, non-volatile embedded flash process technology and an industry-standard 4-input lookup table (LUT) approach for logic implementation. Four density levels have been defined for the family: 256, 640, 1,200, and 2,280 LUT devices, with user I/O counts ranging from 78 to 271. Package options include TQFPs, 8 mm x 8 mm csBGAs, and fpBGAs with 100 to 324 leads. The MachXO1200 and MachXO2280 support one or two analog PLLs, as well as one or three 9-Kb RAM blocks, respectively, yielding 9.2K or 27.6K bits of block memory per device. Prices for the MachXO256 (256 LUT) and MachXO640 (640 LUT) are $1.50 and $2.25 each/250,000, respectively. LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (503) 268-8000