Low-Cost, Ultra-Mini FPGAs Eases Connectivity IF Implementation

A new family of field-programmable gate arrays (FPGAs) from Lattice Semiconductor expands system capabilities and bridges emerging connectivity interfaces using both parallel and serial I/O. The 640-to-22K MachXO3 FPGAs leverage a low-power architecture built on a 40-nm process technology. The logic-cell family employs 2.5- by 2.5-mm wafer-level chip-scale packaging with 540 I/Os—at a cost of about one cent per I/O. Their 3.125-Gbit/s SERDES capabilities cover bridging and interface requirements for consumer, industrial, communications, automotive, and compute applications. An advanced programmable fabric supports up to 150-MHz performance, and includes integrated DSP and memory resources. Multi-time programmable (MTP) technology enables in-field upgrades and instant-on operations. Configuration is possible from a processor or external PROM.

The MIPI-based solutions use hard blocks and soft IP to achieve high-bandwidth programmable bridging for applications, such as 4K by 2K video and 40-Mpixel image-sensor interfaces, and enable access to the latest MIPI-compliant components. High-speed control interfaces and the high-bandwidth data bridges are possible thanks to integrated hard PCIe and Gigabit Ethernet IP. Hot-swap I/O allows components to be swapped out without taking the rest of the system down. The FPGA operate in the automotive and industrial temperature ranges.

LATTICE SEMICONDUCTOR CORP.