Smart Zero Bus Turnaround SRAMs Reduce Potential For Bus Contention

Building upon the original Zero Bus Turnaround (ZBT) architecture developed to provide 100% bus utilization, the latest Smart ZBT SRAMs further simplify system timing requirements and reduce the potential for bus contention. The latest 4-Mb devices are available in pipelined or flow-through versions and are backward compatible with the firm’s existing family of ZBT SRAMs. The ZBT SRAM technology is well suited for systems operating at 133 MHz or slower and that can use less-aggressive ASIC technology or other components such as PLDs having slow turn-off (tCHZ) parameters. The slow turn-off times can delay the ASIC or PLD from getting off a bus that is shared with a fast memory device. The bus contention occurs if the ASIC/PLD does not get off the bus prior to the SRAM getting on. The latest ZBT SRAMs are available in x18- or x36-wide configurations, and interface with 2.5V or 3.3V I/Os.