Digital ICs/DSP: Enhanced FPGA Family Adds 20 Low-Power High-Speed Serial Channels

Feb. 16, 2006

The Stratix II GX family combines the company's fastest and highest-density FPGA fabric (up to 132,540 configurable logic elements and up to 6.7 Mbits of embedded memory) with up to 20 low-power high-speed serial transceivers. Able to operate from 622 Mbits/s to 6.375 Gbits/s, the transceivers consume just 225 mW per channel at 6.375 Gbits/s. They also optimize the data eye opening using on-chip, dynamically programmable transmit pre-emphasis, receive equalization, and output voltage control. The transceiver blocks completely support multiple popular serial protocols. Additionally, designers can complete their designs by utilizing the company's system solutions, which include intellectual property (IP), system models, reference designs, signal integrity tools, and Quartus II v5.1 design tools. In quantities of 25,000 units, prices in mid-2007 will start at $49 each for the EP2SGX30CF780, which has 33,880 logic elements and 1.3 Mbits of embedded memory.

Altera Corp.
www.altera.com/stratix2gx

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.