DSPs Attack Throughput Needs With 600-MHz Clocks And eDRAM

When it comes to executing algorithms in DSP applications, you can never have enough performance. At least that's what designers at Analog Devices must have felt when they collaborated with IBM Microelectronics Corp. to develop the second generation of TigerSharc DSPs. To achieve performance levels of 4.8 billion-integer multiply-accumulates (MACs) and 3.6 billion FLOPS, designers recrafted the DSP core to run at 600 MHz and leveraged IBM's embedded DRAM (eDRAM) capability to pack up to 24 Mbits of storage on the chips.

The three versions of the TS20x series processors, the TS201, 202, and 203, offer 24, 12, and 4 Mbits of on-chip DRAM, respectively. The TS201 can run at 600 MHz, while the other two chips are rated for a top speed of 500 MHz. A quartet of independent 128-bit on-chip buses delivers an aggregate bandwidth of 38.4 Gbytes/s between the various on-chip blocks. The buses connect a pair of complex floating-point MACs, a pair of integer arithmetic logic units (ALUs), and the memory to an I/O processor that controls 14 direct-memory-access channels.

The I/O processor uses low-voltage differential signaling on four external link ports to deliver an I/O bandwidth of 4 Gbytes/s for the TS201 and 202 and 500 Mbytes/s on the TS203. These ports can be used to implement multiprocessor systems with minimal external logic. The floating-point units support both 32- and 40-bit operations, while the integer ALUs support 8-, 16-, 32-, and 64-bit fixed-point computations. The superscalar architecture allows the TigerSharc DSPs to execute up to four instructions per cycle and up to 24 16-bit fixed-point operations or six floating-point operations each cycle.

The complex MACs deliver a throughput of up to 154 complex GMACs. Thus, the TS201 is the only DSP engine able to implement a reconfigurable soft baseband processor for 2G, 2.5G, and 3G wireless basestations. The DSP chips also achieve the high throughput at relatively low power-consumption levels—about 2.5 W when running at 500 MHz.

Two 64-bit interval timers and an IEEE1149.1-compliant JTAG test access port are included as well. Housed in 25-by 25-mm, 576-contact thermally enhanced BGA packages, the TigerSharc processors operate from a 1-V supply and use a 2.5-V supply for the I/O pins.

Samples of the TS201, 202, and 203 are immediately available. They cost $199, $125, and $35 each in lots of 100,000 units.