Digital ICs/DSP: Multichip Module Adds 1 Mbyte Of L2 Cache To PowerPC 755E

Aug. 18, 2005

A multichip package (MCP) solution based around a PowerPC 755E RISC processor provides a compact, high-performance memory solution for space-sensitive, low-power systems. The WED3C755E8M-XBHX combines the PowerPC CPU and a dedicated megabyte of SRAM-based L2 cache (configured as 128 kwords by 72 bits), in a 21- by 25-mm, 255-contact HiTCE package developed by Kyocera. Able to operate at a core frequency/L2 cache frequency of 300/150 MHz or 350/175 MHz, the processor runs a maximum 60X series bus frequency of 66 MHz. Power-management features such as doze, nap, sleep, and dynamic power management let designers minimize system power drain. The MCP is footprint-compatible with previously released 755 and 750-based MCPs as well as with MCPs that use the Freescale MPC 745 PowerPC CPU. (An HiTCE interposer is available for TCE compatibility to laminate substrates.) In lots of 500, the WED3C755E8M-XBHX costs $1000 each. Delivery is eight to 10 weeks.

White Electronic Designs Corp.www.wedc.com

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.