Stiff competition and very high-performance DSPs demanded by emerging convergence applications have motivated Intel Corp. and Analog Devices Inc. to generate a novel DSP core. Using the companies' respective strengths in data- and signal-processing architectures, this core combines the best of DSP and MCU worlds while delivering signal-processing capability unmatched at low power and low supply voltages.
Working on this collaborative DSP project for over a year and a half, the partners have developed a dual-MAC-based micro-signal architecture optimized for high-level language programming. Each MAC can perform a 16- by 16-bit multiply every cycle with a 40-bit accumulation. Also, each of the two 40-bit ALUs operates on either 8-, 16-, 32-, or 40-bit data types (see the figure). The micro-signal architecture is scalable in terms of functional units, so future versions may offer various combinations of MAC, ALU, and shifter functions. No definite plans were unveiled, though.
This project's internal code name, Frio, means "cool" in Spanish. The developers say it remains cool despite its very high-speed processing ability. Initially, the micro-signal DSP core has been implemented in 0.18-µm CMOS. Each company ultimately will use the process that best meets its customers' needs. In effect, each partner will derive a specific core that fits its standard DSP requirements from this architecture.
"The micro-signal architecture will play a vital role in the Intel personal Internet client architecture as we work to speed the development of applications and hardware for next-generation wireless Internet access devices," says Ron Smith, vice president of Intel's wireless communications and computing group. Jerry Fishman, president and CEO of Analog Devices, says, "We will use this new core in chip-set solutions that integrate our high-performance analog, DSP, and RF technologies."
Mark Gill, product-line manager at ADI, says the Frio DSP architecture has been optimized for C/C++ high-level programming languages. This lets designers write both DSP and control code in C. "Consequently," he says, "the optimizing compiler minimizes the use of assembly language required in the production phase of the code." Intel and ADI have readied an advanced compiler for the micro-signal DSP core.
"Its enhanced media instruction set has been tuned for compact code, with code density comparable to the popular ARM7 Thump RISC microprocessor core," Smith notes. To minimize memory usage, the rich instruction set supports 16-bit op-codes for control functions and 32- and 64-bit op-codes for signal processing. Additionally, the micro-signal architecture supports robust operating-system environments, from Linux to simple RTOS solutions.
Besides a dynamic power-management scheme, the micro-signal architecture employs a gated-clock core-design methodology to deliver an order of magnitude improvement in power consumption at a low voltage supply. Actual power-consumption specifications were unavailable at press time. But by adjusting both the voltage delivered to the core and the frequency at which it is running, the dynamic power-management technique optimizes the power delivered for the task.
The first version, designed for a 300-MHz clock, can deliver 600 million MACs/s or 600 DSP MIPS and 2400 MOPS. Its data and code memory bandwidth is specified at 2400 Mbytes/s. Intel and ADI both plan to extend the clock frequency capability to 1 GHz, but this version isn't expected before 2002. The companies also are working with third-party software developers to prepare a development infrastructure for the micro-signal DSP.
Meanwhile, a new generation of cores has been unveiled by Texas Instruments Inc. and StarCore, a research and development initiative between Lucent Technologies' Microelectronics Group and Motorola's Semiconductor Products Sector. The Intel/ADI model looks very similar to Lucent/Motorola's strategy, wherein each partner modifies the jointly developed core to fit its applications.
For more details, point your browser to www.dspjointdevelopment.com.