Digital ICs/DSP: UARTs Run Real-Time Error Detection For Improved Data Integrity

March 15, 2004

Able to perform real-time data error detection on data streams of up to 3 Mbits/s, the SC28L202 dual-channel UART enhances data integrity. It offloads tasks such as parity checking, cyclic redundancy checking, and longitudinal redundancy from the host CPU, freeing the host to perform other tasks. The on-chip FIFO buffers also have been increased to 256 bytes. The larger buffers reduce CPU overhead by minimizing the need for error interrupts (four to 16 times fewer) since designers can set the interrupt level for each FIFO. These buffers also can handle larger packets. The UART operates with either a 3- or 5-V supply from −40°C to 85°C. Housed in a 56-lead TSSOP, the UART costs $6 apiece in lots of 1000 units. Samples are immediately available.

Philips Semiconductorswww.semiconductors.philips.com; (408) 434-3000

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.