Digital ICs/DSP: UARTs Run Real-Time Error Detection For Improved Data Integrity

Able to perform real-time data error detection on data streams of up to 3 Mbits/s, the SC28L202 dual-channel UART enhances data integrity. It offloads tasks such as parity checking, cyclic redundancy checking, and longitudinal redundancy from the host CPU, freeing the host to perform other tasks. The on-chip FIFO buffers also have been increased to 256 bytes. The larger buffers reduce CPU overhead by minimizing the need for error interrupts (four to 16 times fewer) since designers can set the interrupt level for each FIFO. These buffers also can handle larger packets. The UART operates with either a 3- or 5-V supply from −40°C to 85°C. Housed in a 56-lead TSSOP, the UART costs $6 apiece in lots of 1000 units. Samples are immediately available.