Digital ICs/DSP: Programmable Clock Generators Offer In-System Configuration

Aug. 23, 2004

The first devices coming from the ispClock family of in-system programmable clock generator chips combine a high-performance clock generator with a flexible, universal fan-out buffer (UFB). The clock generators in the 10-output ispClock5510 and 20-output ispClock5520 can provide up to five clock frequencies ranging from 10 to 320 MHz. The UFB can drive up to 20 clock nets using either single-ended or differential signaling, with individual output control for improved signal and timing integrity. The UFB has a maximum pin-to-pin skew of 50 ps, while the maximum cycle-cycle (peak-peak) output jitter is less than 100 ps. Housed in a 100-pin TQFP, the ispClock5520 sells for $18.25 each in 1000-unit lots. The PACsystemCLK5520 EV kit costs $349.

Lattice Semiconductor Corp. www.latticesemi.com (503) 268-8000

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.