36-Bit FIFO Memories Target Communications Gear

Targeted at the communications equipment market, the low-density 36-bit SyperSync II FIFO memories operate at 100 MHz and are include features such as bus matching and zero latency transmit. The devices are 3.3V products with 5V-tolerant inputs and are claimed as the industry's first FIFO memories to provide bus matching on both the read and write ports, enabling each port to be configured at a x9, x18 or x36 width. This feature, combined with the chip's independent read and write clocks, is important for datacomm applications where high bandwidth and speed are driving issues in system design. The bus-matching features also makes the devices a cost-effective solution for applications requiring a high-performance, 64-bit microprocessor or a 32-bit DSP.