Digital ICs/DSP: Serial RapidIO Core Proves Itself On FPGA And Structured ASICs

Aug. 18, 2005
A serial RapidIO core, available for use on FPGA platforms or structured or cell-based ASIC designs, has been implemented as a serial RapidIO to PCI bridge. The core has been instantiated in both a structured ASIC from NEC Electronics and an Altera Stra

A serial RapidIO core, available for use on FPGA platforms or structured or cell-based ASIC designs, has been implemented as a serial RapidIO to PCI bridge. The core has been instantiated in both a structured ASIC from NEC Electronics and an Altera Stratix-GX FPGA to prove functionality. Tests undertaken include passing RapidIO traffic between the core and a Fresscale PowerQUICC III processsor through a Tundra Semiconductor Tsi568A switch fabric controlled by Fabric Embedded Tools RapidFET software. The ability of the core to be instantiated on FPGA or various ASIC technologies enables designers to prototype systems in a flexible, low-cost environment before transferring the design to production. Contact the company for licensing terms.

Jennic Ltd.www.jennic.com
About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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