If you've grown tired of purchasing premium FPGAs to gain the benefit of a
full-rate SPI-4.2 bridge core supporting complex packet flow and traffic management,
consider the Economy Plus 2 (ECP2) family from Lattice Semiconductor.
With up to 70K look-up tables (LUTs) at your disposal, the fewer than 5K LUTs
required for a soft IP core that fully complies with the Optical Internet-working
Forum's SPI-4.2 standard will leave you with plenty of extra logic to work with.
The SPI-4.2 core operates at interface speeds of up to 750 Mbits/s while fulfilling
all requirements of the SPI-4.2 interface protocol, including support for up
to 256 logic channels, calendars, transmit and receive status, programmable
burst size, and DIP4 error checking.
Also, the SPI-4.2 operates at up to 10 Gbits/s, suiting it for the telecom/
datacom markets and applications such as network processors, traffic managers,
media access controllers (MACs)
Based on 90-nm technology, the ECP2 FPGA includes features such as high-performance DSP blocks, support for dual data rate (DDR) 1 and 2 memory interfaces at up to 400 Mbits/s and up to 840 Mbits/s LVDS performance.
Other enhanced features include the following
- A dual boot operation that supports the storage of multiple configurations
in SPI memory. This is particularly useful for systems that are field updated.
- An AES-128 compliant encryption scheme that provides non-volatile memory
for key storage. This feature will help secure designs and deter design piracy.
- The ability to freeze I/O states during configuration. Named "TransFR IO,"
this feature allows for in-system field updates while minimizing system disruption
and downtime.
The I/O cells in the ECP2 family offer a number of pre-engineered elements for simple implementation of source synchronous interfaces. These elements include dedicated precision DQS/strobe delay control, dedicated DDR I/O registers for multiplexing and de-multiplexing data, automatic DQS to system clock domain transfer, gearbox logic to match the I/O speed with the FPGA fabric performance, and low skew edge clocks. These elements can be easily configured in Lattice's ispLEVER design tool to implement a variety of high-performance interfaces.
Some of the ECP2 devices are now in limited production, with availability of most family devices due by year's end.
The ECP2-50 costs $23.95 in quantities of 100,000. Lattice's SPI-4.2 soft IP
core for the ECP2 is available now. The netlist version lists for $15,000.
Lattice Semiconductor
www.latticesemi.com
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