PLD Design Suite Evolves To Next Level

Version 5.1 of the ispLEVER programmable logic design suite adds features that include a FPGA preference flow, enhanced timing-closure and design-fit capabilities, and an IP-delivery infrastructure (IPexpress) that allows quick configuration of the system-level IP. The FPGA design preference flow provides more control, allowing users to make preference changes at any point in the design process. IPexpress Infrastructure promises to accelerate the development of IP parameters by providing a single gateway to standard, user-configurable functions. Other enhancements include updated versions of Synplicity Synplify for Lattice (v8.2c), and Precision RTL (2005b) synthesis and ModelSim version 6.1a simulation tools from Mentor Graphics. Additionally, the software expands device libraries to support more EDA tools, including simulation and DSP design elements for the MATLAB/Simulink design environment. Price for ispLEVER 5.1 is $695. For more details, contact Brian Kiernan at LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (503) 268-8739.