Advanced 90-nm Process Packs 400 Million Transistors On-Chip

March 18, 2002
With over 400 million transistors on a single chip, Texas Instruments' next-generation 90-nm (0.09-µm) CMOS process will enable TI to pack DSP, microcontroller, memory, logic, analog, and RF functions on one CMOS die, with moderate power...

With over 400 million transistors on a single chip, Texas Instruments' next-generation 90-nm (0.09-µm) CMOS process will enable TI to pack DSP, microcontroller, memory, logic, analog, and RF functions on one CMOS die, with moderate power consumption. The process targets upcoming multigigahertz DSPs, UltraSparc processors, and highly integrated systems-on-a-chip (SoCs).

By permitting adjustment of transistors' gate lengths, threshold voltages, gate-oxide thickness, or bias conditions, the process makes possible transistors tuned for different functions on one chip. As a result, transistors with the highest performance can be used in performance-critical functions like signal processing, while those with lower power consumption can support stringent active and standby power needs. TI expects at least two-fold cut in power consumption.

The 90-nm process combines copper interconnects and low-k dielectric material with the highest SRAM density and transistors with 37-nm gate lengths. Depending on the applications, TI will offer gate lengths ranging from 70 to 37 nm. The 37-nm gate-length transistor will incorporate 1.3-nm gate oxide thickness (see the photo).

The process uses up to nine layers of copper interconnect and organo-silicate glass with a dielectric constant of 2.8. While the core voltage will drop to 1.1 V, clever back-biasing will increase the effective threshold voltage. By comparison, TI's current-generation 130-nm CMOS process uses a 1.2-V core voltage.

Aimed at 2.5G and 3.0G cell phones, the new process will enable the convergence of applications by integrating low-voltage PDA, MP3 player, and cell-phone functions on one chip. On-chip multiprocessing will be common at the 90-nm node, as it will allow multiple DSP cores and a large amount of memory to be integrated on the same chip. Also, the 90-nm process will boost the raw speed of DSPs by 25%.

The 90-nm process is being developed for both 200- and 300-mm wafer fabrication. Prototypes based on this process will be unwrapped by the first quarter of 2003. And, it is expected to go into production by the third quarter of 2003.

For more information, visit www.ti.com.

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