Digital ICs/DSPs: Regsitered Buffers Take On DDR2 Loads Up To 450 MHz

Dec. 8, 2004

The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer designed for 1.7- to 1.9-V VDD operation at clock frequencies of up to 450 MHz. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The...

Dave Bursky

The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer designed for 1.7- to 1.9-V V_DD operation at clock frequencies of up to 450 MHz. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All 1.8-V, CMOS-driver outputs are optimized to drive the DDR2 dual-inline memory module load. Operating from a differential clock (CK and CK—), the buffer locks in data at the crossing point when CK goes HIGH and CK— goes LOW. The device supports low-power standby operation. When the reset input is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. The buffer is housed in a 96-ball, 13.5- by 5.5-mm, low-profile, fine-pitch ball-grid-array package. In quantities of 10,000 units, the buffer is priced at $4.35 each.

Philips Semiconductors
www.philipssemiconductors.com

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.