Enhanced Core Plus New Features Equals Video-Optimized DSP

Improved execution efficiency and code storage density--thanks to an enhanced instruction-set architecture--catapults the TMS320C6455 DSP to a 20% average throughput upgrade over its predecessor, the C6415 DSP. The greater performance ushers in more bandwidth to handle HDTV or standard video signals.

The enhanced instruction set includes 16-bit operations to reduce code size by 20% to 30%. In addition, TI claims the C6455 is the first DSP chip to pack both Serial RapidIO links and a 1-Gbit Ethernet media access controller. The chip integrates dual DDR2 memory controllers (up to DDR2-500), 2 Mbytes of L2 memory, dual 32-kbyte L1 caches, and a 64-bit legacy memory interface to allow easy upgrades from systems using previous-generation DSPs.

To speed large array computations, the chip can deliver twice as much multiply bandwidth as previous DSPs thanks to its ability to perform eight 16- by 16-bit multiply-accumulate operations per cycle. The four on-chip Serial RapidIO links provide an aggregate bidirectional throughput of 25 Gbits/s, permitting high-speed DSP-to-DSP and DSP-to-switch data transfers. A 1x link is fast enough to send a 1080i HD raw video data stream between devices, while the full 4x link can handle 1080p HD raw video data. Even though the new chip sports an enhanced instruction set, software written for previous-generation TI DSPs can run on the C6455.

Development tools are available now. Engineering samples of the pre-production chip are scheduled for the third quarter. Full production versions will be ready in the second quarter of 2006. In lots of 10,000 units, the C6455 sells for $179, $219, or $259 apiece, depending on the speed grade--720 MHz, 850 MHz, or 1 GHz, respectively.