Digital circuits such as CPUs and SoCs will gain the most from these techniques. However, FPGAs and memory devices also will achieve new highs in density thanks to scaled-down process features.
In the DRAM arena, 512-Mbit and 1-Gbit devices are now commodity devices. But the push for 2- or 4-Gbit DRAMs isn't quite there yet. Instead, most DRAM vendors are focused on defining and implementing the next-generation interface?DDR3.
In addition, many designers are focused on bringing the fully buffered dual-in-line memory module (FB DIMM) up to full production. Such devices address the limitations of systems that would like to employ more than four registered DIMMs on a single double-data-rate (DDR) memory controller. With more than four registered DIMMs, the bus loading degrades performance. In the FB DIMM approach, it's possible to implement much larger memory systems.
In flash memory, size is everything as more and more applications lean more heavily on nonvolatile storage. The larger the capacity, the better?as long as it's cheap. Therefore, flash-device manufacturers have been the most aggressive when applying process scaling to their memory designs.
Today, Samsung produces 16-Gbit monolithic flash memories and expects to further scale its technology to craft 32-Gbit devices in 2007. Other flash vendors, such as STMicroelectronics and Toshiba, now feature 4- and 8-Gbit devices.
Its hard to pick up any comunications or entertainment product that doesn't include some form of DSP, whether it's embedded in a larger SoC or as a standalone coprocessor or main processor in the system. Multicore and very-long-instruction-word approaches in DSP chips are still the mainstream approach to improve performance. That's because DSP algorithms often can complete many operations in parallel.