Quad-Core DSP Targets Multimedia And Wireless Infrastructure
Multimedia and wireless infrastructure platforms require massive amounts of compute power—just like the kind that the MSC8144 from Freescale Semiconductor can deliver.
This silicon-on-insulator (SOI) chip uses 90-nm technology. On-chip interfaces include an eight-port, 2048-channel time-division multiplexing (TDM) unit and a 1x/4x Serial RapidIO (SRIO). The chip also features a pair of Gigabit Ethernet interfaces and a 500-MHz Utopia interface. The lower-speed UART and I2C are primarily for configuration and diagnostics.
The system's power comes from a combination of the four 1-GHz StarCore processors and a very large amount of on-chip memory. The chip offers 512 kbytes of fast M2 memory and 16 Mbytes of M3 memory. The on-chip memory reduces or eliminates the need for off-chip RAM. This memory sits above the L1 and L2 caches. All of the processors-share the L2 instruction cache. A high-speed, non-blocking switch fabric ties the processors, memory, and peripherals together.
The processor cores are based on Freescale's SC3400 third-generation StarCore architecture. Each unit can write trace information directly to the M2 memory. Each unit also incorporates a number of features designed to enhance processing in the target environment. Hardware-based scheduling enhances quality-of-service and streamlines load balancing among the cores.
L2 cache interleaving boosts the transparent speed. A hardware-based background cache sweep mechanism helps prevent pipeline stalls. DMA interrupt, chaining, and overhead reduction help decrease application overhead, especially for video applications. And, better DMA granularity improves operation with SDRAM.
The JTAG diagnostic interface can single-step the chip. All other diagnostic tools are available through the high-speed SRIO and Gigabit Ethernet interfaces.
Pricing for the MSC8144 starts at $180. It's available in a 29- by 29-mm flip-chip plastic ball-grid array package.
Freescale Semiconductor
www.freescale.com
