FPGA Design Tool Aids In I/O Assignments

March 22, 2007

The latest version of Xilinx’s PlanAhead hierarchical FPGA design and analysis software sports support for the company’s 65-nm Virtex-5 and Spartan-3 devices. Used with the Xilinx Integrated Software Environment (ISE), PlanAhead 9.1 gives designers a new means of wringing the most out of their creations. By exploiting the Virtex-5 ExpressFabric technology, 550-MHz DSP48E slices, and flexible clock management tiles, the PlanAhead 9.1 design suite delivers as much as a two-speed-grade advantage over competitive offerings.

PlanAhead 9.1 includes a new PinAhead Technology, offering an environment for fully automatic or semi-automated assignment of I/O ports to physical package pins. Using PinAhead Technology, FPGA designers can assign interface I/O groups to I/O pins simply by dragging them into a graphical representation of the FPGA.

PinAhead Technology provides an interface to analyze the design and device I/O requirements and to define an I/O pinout configuration that satisfies the needs of both the PCB and FPGA designers. Designers can begin pin assignment prior to having a completed PCB or FPGA netlist, drastically reducing time-to-market. PlanAhead 9.1 allows designers to either create their own port list with a GUI interface or import a comma-separated-values (CSV) spreadsheet. This allows early decisions to be made permitting the PCB and FPGA designers to begin work much earlier with a much more realistic pinout configuration.

Additionally, PinAhead technology allows early and intelligent pinout definition to eliminate many of the pinout-related changes that typically happen downstream. Better user control of FPGA pinout early in the design process can also offer significant improvements in performance, avoiding a non-optimal pinout that causes further delays when trying to meet timing requirements. By considering the data flow from PCB to FPGA die, optimal pinout configurations can be achieved quickly, thus reducing internal and external trace lengths and routing congestion.

To help users better manage dynamic placement constraints, which may be user assigned or imported from the netlist generated by the ISE design tools, PlanAhead 9.1 provides a simplified method for controlling constraints. Designers are now able to clear placement constraints assigned by the ISE Design Tools without affecting remaining user constraints. Designers also have the ability to selectively mark a subset of the placement constraints assigned by the ISE implementation tools to be treated as user defined constraints. The capability with PlanAhead 9.1 to better control logic preservation provides ultimate flexibility while keeping the process intuitive.

In addition to supporting the latest Virtex-5 LX, LXT, and SXT devices, PlanAhead 9.1 software extends device support to the company's latest Spartan-3 generation FPGAs including the recently introduced I/O-optimized Spartan-3A and non-volatile Spartan-3AN platforms.

The PlanAhead 9.1 design suite is available on all major operating systems as an option to the Xilinx ISE design suite. Single-user licenses are currently available at a promotional price of $2495 U.S. list.

For more information, visit http://www.xilinx.com/planahead .

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.