Flow Implements C++ DSP Algorithms in FPGAs
Using a design flow put together by Mentor Graphics and Altera, designers can implement complex DSP algorithms in high-performance FPGAs directly from ANSI C++ code. The flow, which is based on Altera’s Accelerated Libraries for Mentor Graphics’ Catapult C synthesis tool, is said to deliver 50-80% DSP Fmax performance improvements.
The Catapult C/Altera DSP design flow is a C-to-RTL design flow that closely resembles the traditional DSP software programming flow. In both flows, algorithm designers develop a floating-point model of an algorithm, and then convert that to a fixed-point model, typically in C++. At this point in the traditional flow, software developers compile the C code for an off-the-shelf DSP. With the Catapult C/Altera flow, a hardware designer would use the Catapult C synthesis tool with Altera’s Accelerated Libraries to automatically create a DSP hardware implementation for an Altera FPGA.
Unlike before, the hardware designer does not need to manually write the RTL code, worry about hand-coded errors, or re-write RTL code numerous times to find an architecture that delivers reasonable performance. The Catapult C/Altera solution automates the RTL creation process, delivering hardware performance with the flexibility of a DSP software programming flow.
Contact Altera and/or Mentor Graphics directly for information on pricing and delivery.
Altera
Mentor Graphics