MIPS64 Core Handles Up To 450 MIPS

A 64-bit synthesizable processor core, the MIPS64 5Kc delivers up to 450 MIPS for networking, digital consumer, and office automation applications. Suitable for system-on-chip (SOC) or SOC ASIC integration, the core is compatible with existing MIPS-based IP to provide an upgrade path for designers. The MIPS64 architecture is designed for IP re-use and software compatibility between 32- and 64-bit processor platforms. This standardizes the MIPS RISC processor architecture and enables real-time operating systems, cache control code, start routines, and application code to be developed once and executed on any MIPS32/MIPS64 compliant processor. The MIPS64 5Kc processor core is a fully static design and includes several power saving modes to bring power consumption down to 1 mW/Hz when using a 0.15-micron process CMOS technology.