SHARC DSP Sets MFLOPS/s Performance Mark

The ADSP-21161 SHARC DSP is capable of 600 MFLOPS/s, what is said to be more than three times the performance for comparable devices at about the same price. The device integrates 1 Mb of dual ported SRAM and the company's multiprocessor interfacing technology.
Based on the SIMD SHARC core that supports single-instruction, multiple data execution of 32-bit fixed and floating point arithmetic, the chip features 14 direct memory access (DMA) channels, two 128-channel synchronous TDM and four I2S serial ports, a 32-bit parallel port that includes a 32-bit SDRAM controller, and an SPI interface. Clusters of DSPs can be built using the on-chip multiprocessing interfaces and connection of up to six SHARC DSPs and a host can be achieved without the need to design external circuitry. The device also provides hardware and software compatibility with over 70 multiprocessing design tools available from third parties and is 5.0 volt-tolerant for I/O.
Manufactured with a state-of-the-art .18µ CMOS process, price for the 100 MHz ADSP-21161NKB-100X, 225-BGA (ball grid array) is $35 each/1,000.