Chips Handle High-Speed Signal Processing Assignments At Low Power And Cost

The TMS320C55x digital signal processor architecture has been tapped to construct two new DSP chips whose performance and cost are expected to garner for the devices a host of design wins in embedded telecomm, consumer audio, medical, biometric, and industrial sensing applications. Operating at speeds of 300 MHz, the TMS320VC5501 and TMS320VC5502 are dual-MAC DSPs that dissipate a mere 194 mW and feature 16 Kb of instruction cache, 32 KB of core ROM, and a shared core data and program memory scheme (32 KB of DARAM for the C5501 and 64 KB for the C5502) that reduces latencies and expands external memory options compared to a separate scheme. The C5501 and C5502 DSPs also pack a 16- and 32-bit external memory interface (EMIF), respectively, and an 8- and 16-/8-bit enhanced host port interface. The chips also boast of a 6-channel DMA, I2C multi-master and slave interface, hardware UART, programmable phase-locked loop (PLL) with on-chip oscillator, three timers (two general-purpose), one programmable watchdog, and 76 GPIOs (eight dedicated). Other features expected to help the 300-MHz DSPs gain the designer’s attention are code compatibility with an extensive array of existing C5000 devices, an extended operating temperature range of -40°C to +85°C, availability in both 176-pin LQFP and MicroStar BGA packages, and 10K prices of $5 (C5501) and $9.95 (C5502). A 200-MHz version of the latter is also available. Sampling of the C5501 is to begin in Q3 of 2003, with production to start in Q4 of 2003; the C5502 is sampling now and will be produced in volume in Q3 of 2003. TEXAS INSTRUMENTS INC., Dallas, TX. (800) 477-8924.