Forecasting remarkable capabilities in code efficiency, processing performance, and power consumption, the company's design for a Complex Instruction Set Computer (CISC) CPU architecture will soon take form in the next generation RX family of MCUs.
Forecasting remarkable capabilities in code efficiency, processing performance, and power consumption, the company's design for a Complex Instruction Set Computer (CISC) CPU architecture will soon take form in the next generation RX family of MCUs. The family includes 16- and 32-bit versions of the CISC CPU core with a maximum operating frequency of 200 MHz. Users can expect processing performance in the realm of 1.25 MIPS/MHz, a 30% reduction in object-code size, power consumption of 0.03 mA/MHz, plus compatibility and scalability with the company's existing products. For more information, call RENESAS TECHNOLOGY AMERICA INC., San Jose, CA. (408) 382-7407.
