High-density (serial or parallel programmable) concurrent flash memory, complex programmable logic, SRAM, extra I/O and a programmable MCU interface are all integrated within the PSD8XXF2 flash MCU support IC. The device allows flash to be erased or written to during program execution by providing two flash-memory arrays of 128 kbytes and 32 kbytes. The former holds system programs; the latter, which is partitioned into four 8-kbyte sectors, is for storage of boot algorithms, programming algorithms and non-volatile memory data. Because the system can execute code from either array, each can be programmed concurrently with system operation. As a result, concurrent parallel in-system programming is made possible without resorting to an external boot device.In addition to the two flash arrays, the device has a 2-kbyte scratchpad SRAM, a 3000-gate Micro-Cell CPLD, a special ISP decoding PLD, extra I/O and a programmable interface to most MCUs from Intel, Motorola, Philips, Siemens, and others.
Company: WAFERSCALE INTEGRATION INC. (WSI)
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