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AMD Releases 12-core "Magny Cours" Opteron 6100 Series

April 2, 2010
AMD ups the ante on servers with its 12-core Opteron 6100 Series. The chips now have four memory channels and 4.8 Gtransfers/s.

12-core "Magny Cours" Opteron 6100 Series

Opteron 6100 Series 4P configuration

AMD ups the ante on servers with its 45nm, 12-core Opteron 6100 Series. The chips now have four memory channels and 6.4 Gtransfers/s Hyperchannel links. It can support 48 DIMMs in a 4P configuration. Its Direct Connect Architecture 2.0 has only one hop between processors in a 4P configuration. The 346mm2 die has 1.8 trillion transistors.

The Direct Connect Architecture 2.0 delivers a total cache size of 19.6 Mbytes in a 12-core chip (128 kbytes L1, 512 kbyts/core L2, 12 Mbytes L3/chip). It adds a fourth Hypertransport link allowing significantly larger multichip servers with fewer hops between processors.

The four memory controllers support up to 42.7 Gbytes/s of memory bandwidth. The chips also support the low voltage, 1066 MHz LV-DDR3 memory.

AMD has also added the C1E power state. This very low power state is used when all cores are idle. The power management system has also been improved so it reduces p-states when a preset temperature limit is reached. The Advanced Platform Management Link (APML) allows better remote power management using PTM (Predictive Technology Model) and RPMI (Remote Power Management Interface).

AMD says is has removed the "4P tax" where there was a significant jump in price from a 2P to a 4P system. Part of this is due to the number of Hyperchannels on the chips since it is now just as easy to construct a 2P as a 4P system. Just add sockets.

Pricing starts at $455 for the 1.8 GHz, 8-core 6124HE with a 65W ACP (Average CPU Power) ending up at the $1386 12-core, 2.3 GHz 6176 SE with a 105W ACP. The chips use the Socket G34 with 1994-pin organic Land Grid Array (LGA).

AMD

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William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

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